As display panels get bigger, the amount of current running through the source driver that drives the display panel is increased. As the amount of current increases, so does the amount of heat generated by the source driver.
FIG. 1 is a block diagram of a conventional prior art display device 10. As shown in FIG. 1, the display device 10 comprises a display panel 20, a data line driver (or source driver) 30, a scan line driver (or gate driver) 50 and a controller 60. The display panel 20 further includes a plurality of source lines S1, S2, . . . Sn, a plurality of gate lines G1, G2, . . . Gm and a plurality of pixel electrodes (not shown in FIG. 1).
The source driver 30 drives the source lines (or data lines) S1, S2, . . . Sn of the display panel 20 based on digital image data DATA that is output from the controller 60. The source driver 30 may comprise, for example, a shift register (not shown in FIG. 1), a line latch (not shown in FIG. 1), a digital-to-analog converter 31 and an output buffer array 32.
The digital-to-analog converter 31 generates a plurality of analog voltages IN1, IN2, . . . INn in response to the digital image data DATA. The output buffer array 32 buffers the analog voltages output from the digital-to-analog converter 31, and outputs corresponding analog voltages to the source lines S1, S2, . . . Sn. The output buffer array 32 comprises a plurality of output buffers 33, 34, . . . 35, each of which buffers a corresponding analog voltage output from the digital-to-analog converter 31 and outputs the buffered analog voltage to a corresponding source line S1, S2, . . . Sn.
The gate driver 50 sequentially drives the gate lines (or scan lines) G1, G2, . . . Gm of the display panel 20 under control of the controller 60. The controller 60 controls the operation of the source driver 30 and the gate driver 50. The controller 60 may be under the control of a host computer.
FIG. 2 is a circuit diagram of one of the output buffers (output buffer 33) of FIG. 1. FIG. 3 is a timing diagram of the input/output signals of the output buffer 33 shown in FIG. 2. Referring to FIGS. 1-3, the first switching signal SW and the second switching signal CS are predetermined switching signals generated in the source driver 30. AMP_OUT is the output voltage of a unit gain buffer 41, and OPSC is the static current consumed in the output buffer 33. TCR is the total current consumed in the output buffer 33, and TPW is the total power consumed in the output buffer 33.
Generally, the output voltage OUT of the output buffer 33 in the source driver 30 is output synchronously with the first clock signal CLK1 (see FIG. 3). During the high cycle of the first clock signal CLK1, the output voltage OUT of the output buffer 33 is supplied to the source line S1 of the display panel 20 or during the low cycle of the first clock signal CLK1, the output voltage OUT of the output buffer 33 is supplied to the source line S1 of the display panel 20. As shown in FIGS. 2-3, during the high cycle of the first clock signal CLK1, a first transmission gate 42 is off in response to a first switching signal SW and a second transmission gate 43 is on in response to a second switching signal CS. As such, the output terminals of the output buffers 33, 34, . . . 35 are connected to each other through the second transmission gate 43. Consequently, the output terminals of the output buffers 33, 34, . . . 35 share a load (not shown) that is connected to the source lines. Thus, the high duration of the first clock signal CLK1 is called a charge sharing region CSR.
During the low cycle of the first clock signal CLK1, the first transmission gate 42 is on in response to the first switching signal SW, and the second transmission gate 43 is off in response to the second switching signal CS. As a result, each of the output buffers 33, 34, . . . 35 has characteristics corresponding to specification and charges the load connected to the source lines of the display panel 20 with a prescribed amount of charge.
As shown in FIG. 3, the output buffer 33 rapidly charges the load connected to the source line S1 of the display panel 20 with a predetermined amount of charge in an operating region OR. Once the load is sufficiently charged, the output buffer 33 charges the load with a small amount of charge in a standby region SR. Herein, the operating region OR refers to the region in which the load is rapidly charged with the output charge from the output buffer 33, and the standby region SR refers to the region in which the output buffer 33 charges the load with only a small amount of charge, or maintains the charged level of the load at a desired level.